With recent development of relevant technologies, semiconductor devices continuously advance toward higher integration and higher speed and are used in a variety of products from large home appliances to small mobile products.
In general, semiconductor devices are designed with an objective to consume less power and realize higher operation speed. To this end, the semiconductor memory device is provided with a power down mode which stops operation of internal circuits including an address buffer and a command buffer, to reduce unnecessary current consumption when the semiconductor device is maintained in a standby state for a certain period.
This power down mode will be described with reference to FIG. 1.
FIG. 1 is a block diagram illustrating a conventional input circuit of a semiconductor memory device.
The input circuit includes an address buffer 500 and a command buffer 600.
The address buffer 500 buffers external address signals ADD<1:4> in response to an internal clock ICLK to generate internal address signals IADD<1:4>.
The command buffer 600 buffers a chip selection signal /CS, a RAS signal /RAS, a CAS signal /CAS and a write enable signal /WE in response to the internal clock ICLK to generate an internal chip selection signal /ICS, an internal RAS signal /IRAS, an internal CAS signal /ICAS and an internal write enable signal /IWE. As described above, the address buffer 500 and the command buffer 600 receive external signals in synchronization with the internal clock ICLK to generate internal signals.
When the address buffer 500 and command buffer 600 enter into a power down mode, the internal clock ICLK is disabled and operations of the address buffer 500 and the command buffer 600 are stopped. That is to say, unnecessary current consumption of the address buffer 500 and the command buffer 600 is reduced upon the power down mode.
Meanwhile, when the power down mode is ended and the address buffer 500 and the command buffer 600 enter into the non power down mode, the internal clock ICLK is enabled and the operation of the address buffer 500 and the command buffer 600 are resumed. In the non power down mode, the semiconductor memory device performs read operation, write operation and precharge operation according to the external command, and the address buffer 500 and the command buffer 600 are maintained in the activation state regardless of whether the external command is inputted or not since the internal clock ICLK is in an enabled state. That is to say, continuous current consumption is generated through the address buffer 500 and the command buffer 600 during the non power down mode. Particularly, as a memory capacity of a semiconductor memory device is increased, the number of the external address signal and the number of the address buffer for buffering the external address signal are also increased to result in unnecessary consumption of more current.